-------------------------------------------------------------------------------
-- Title      : Button debouncer for Nexys 2 push buttons
-- Project    : 
-------------------------------------------------------------------------------
-- File       : debounceBits.vhd
-- Author     : Paul W
-- Company    : 
-- Created    : 2012-09-30
-- Last update: 2012-12-12
-- Platform   : 
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Edge detect an input. Register the input at the in_sample
--              interval and output high for only one tick while the input
--              stays high.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2012-09-30  1.0      paul	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity debounceBits is
  generic (
    WIDTH : integer := 4);
  
  port (
    in_clk    : in  std_logic;
    in_sample : in  std_logic;
    in_bits   : in  std_logic_vector(WIDTH-1 downto 0);
    out_bits  : out std_logic_vector(WIDTH-1 downto 0));

end entity debounceBits;

architecture rtl of debounceBits is

  signal bits_d1  : std_logic_vector(WIDTH-1 downto 0);
  signal bits_d2  : std_logic_vector(WIDTH-1 downto 0);
  signal bits_out : std_logic_vector(WIDTH-1 downto 0);

begin  -- architecture rtl

  -- Debounce the bits with FFs at the in_sample determined interval
  -- NOTE: No rst is used, as a button is often a rst generator
  debouncer_proc : process (in_clk) is
  begin  -- process debouncer_proc
    if rising_edge(in_clk) then         -- rising clock edge
      bits_out <= (others => '0');
      if in_sample = '1' then
        bits_d1 <= in_bits;
        bits_d2 <= bits_d1;
        for ii in WIDTH-1 downto 0 loop
          if bits_d2(ii) = '0' and bits_d1(ii) = '1' then
            bits_out(ii) <= '1';
          end if;
        end loop;  -- ii
      end if;
    end if;
  end process debouncer_proc;

  -- Map the debounced signal out
  out_bits <= bits_out;
  
end architecture rtl;
